.include
"8535def.inc"
.def
temp=r16
.def
cnt=R17
.def
count=R18
.def
temph=R25
.def
resl=R13
.def
resm=R14
.def
resh=R15
.equ
q1=4
.equ
q2=5
.equ
K=60
.equ ed=400
.equ des=40
.org 0
rjmp RESET ; Reset
Handler
rjmp EXT_INT0 ; IRQ0
Handler
rjmp EXT_INT1 ; IRQ1
Handler
rjmp TIM2_COMP ;
Timer2 Compare Handler
rjmp TIM2_OVF ; Timer2
Overflow Handler
rjmp
TIM1_CAPT ; Timer1 Capture Handler
rjmp
TIM1_COMPA ; Timer1 CompareA Handler
rjmp
TIM1_COMPB ; Timer1 CompareB Handler
rjmp
TIM1_OVF ; Timer1 Overflow Handler
rjmp
TIM0_OVF ; Timer0 Overflow Handler
rjmp
SPI_STC; ; SPI Transfer Complete Handler
rjmp
UART_RXC ; UART RX Complete Handler
rjmp
UART_DRE ; UDR Empty Handler
rjmp
UART_TXC ; UART TX Complete Handler
rjmp
ADCcomplete ; ADC Conversion Complete Interrupt Handler
rjmp
EE_RDY ; EEPROM Ready Handler
rjmp
ANA_COMP ; Analog Comparator Handler
RESET:
ldi
temp, high(RAMEND);
out
SPH,temp;
ldi
temp, low(RAMEND) ;
out
SPL,temp;
ldi
temp,2
out
ADMUX,temp
ldi
temp,(1<<ADEN|1<<ADSC|0<<ADFR|1<<ADIE|1<<ADPS2|1<<ADPS1|0<<ADPS0);
out
ADCSR,temp;
ldi
temp,(1<<OCIE1A);
out
TIMSK,temp
ldi
ZH, high (K)
ldi
ZL, low (K)
clr
count
ldi
cnt,2
sei;
Start:
rjmp
start
EXT_INT0:
reti
;
EXT_INT1:
reti
;
TIM2_COMP:
reti
;
TIM2_OVF:
reti
;
TIM1_CAPT:
reti
;
TIM1_COMPA:
in
temp,ADCL;
ld
temph,Z
add
temp,temph
st
Z+,temp
in
temp,ADCH;
ld
temph,Z
adc
temp,temph
st
Z+,temp
tst
cnt
breq
nstep
ldi
cnt, 3
ldi
ZH, high (K)
ldi
ZL, low (K)
inc
count
cpi
count,16
breq
sred
nstep:
dec
cnt
out
ADMUX,cnt
ldi
temp,(1<<ADEN|1<<ADSC|0<<ADFR|1<<ADIE|1<<ADPS2|1<<ADPS1|0<<ADPS0);
out
ADCSR,temp;
reti;
sred:
dec
cnt
ld
temp, Z
ldd
temph, Z+1
swap
temp
andi
temp,0b00001111
swap
temph
std
Z+1,temph
andi
temph,0b11110000
or
temp,temph
st
Z+,temp
ld
temph, Z
andi
temph,0b00000011;
st
Z+,temph
clr
resh
clr
resm
clr
resl
edinicy:
cpi
temph,high(ed)
brlo
desyatue
brne
sub_ed
cpi
temp,low(ed)
brlo
desyatue
sub_ed:
subi
temp,low(ed)
sbci
temph,high(ed)
inc
resh
rjmp edinicy
desyatue:
cpi temp,des
brlo sotue
sub_des:
subi temp,des
inc resm
rjmp desyatue
sotue:
lsr temp
lsr temp
mov resl,temp
swap resm
mov temp,resm
or resl,temp
std Z+q1,resl
std Z+q2,resh
tst cnt
brne
sred
clr
count
st
-Z,count
st
-Z,count
st
-Z,count
st
-Z,count
st
-Z,count
st
-Z,count
ldi
cnt,2
out
ADMUX,cnt
ldi
temp,(1<<ADEN|1<<ADSC|0<<ADFR|1<<ADIE|1<<ADPS2|1<<ADPS1|0<<ADPS0);
out
ADCSR,temp;
reti
;
TIM1_COMPB:
reti
;
TIM1_OVF:
reti
;
TIM0_OVF:
reti ;
SPI_STC:
reti
UART_RXC:
reti
UART_DRE:
reti
UART_TXC:
reti
ADCcomplete:
reti
EE_RDY:
reti
ANA_COMP:
reti
|