|
.include
"8535def.inc"
.def temp=r16
.def cnt=R17
.def sum_r=R18
.def sum_t=R20
.def txden=R19
.def txtmp=R21
.def cnt_byte=R22
.def cnt_bit=R23
.def cnt_tx=R24
.def len_r=R25
.def len_t=R26
.def dat_t=R15
.equ conv=556
.equ shft=0x20
.equ addr=0x60
.equ strt=0x55
.org 0
rjmp RESET ; Reset Handler
rjmp EXT_INT0 ; IRQ0
Handler
rjmp EXT_INT1 ; IRQ1
Handler
rjmp TIM2_COMP ; Timer2
Compare Handler
rjmp TIM2_OVF ; Timer2
Overflow Handler
rjmp TIM1_CAPT ; Timer1
Capture Handler
rjmp TIM1_COMPA ; Timer1
CompareA Handler
rjmp TIM1_COMPB ; Timer1
CompareB Handler
rjmp TIM1_OVF ; Timer1
Overflow Handler
rjmp TIM0_OVF ; Timer0
Overflow Handler
rjmp SPI_STC; ; SPI
Transfer Complete Handler
rjmp UART_RXC ; UART RX
Complete Handler
rjmp UART_DRE ; UDR Empty
Handler
rjmp UART_TXC ; UART TX
Complete Handler
rjmp ADCcomplete ; ADC
Conversion Complete Interrupt Handler
rjmp EE_RDY ; EEPROM Ready
Handler
rjmp ANA_COMP ; Analog
Comparator Handler
RESET:
ldi temp, high(RAMEND);
out SPH,temp;
ldi temp, low(RAMEND) ;
out SPL,temp;
ldi temp,
(1<<PD1|0<<PD0); RxD(PD0) - input, TxD(PD1) - output
out DDRD, temp
ser temp
out PORTD, temp ; PD1=1
ldi temp,
(1<<RXCIE|1<<RXEN)
out UCR, temp ; 8-bit, recieve
ldi temp, 34
out UBRR, temp ; 14400 bod
clr cnt
clr sum_r
clr sum_t
ldi YL, addr
ldi ZL, addr+shft
ldi temp,(1<<CTC1|1<<CS10); 14400Hz, transfer
out TCCR1B,temp
ldi temp, high(conv)
out OCR1AH,temp
ldi temp, low(conv)
out OCR1AL,temp
clr txden
ldi temp,
(1<<OCIE1A)
out TIMSK, temp
sei;
Start:
rjmp start
EXT_INT0:
reti
EXT_INT1:
reti
TIM1_CAPT:
reti ;
TIM2_COMP:
reti
TIM2_OVF:
reti
TIM1_OVF:
reti
TIM1_COMPB:
reti
TIM0_OVF:
reti ;
SPI_STC:
reti
UART_DRE:
reti
UART_TXC:
reti
ADCcomplete:
reti
EE_RDY:
reti
ANA_COMP:
reti
TIM1_COMPA:
sbrs txden,0
reti
cpi cnt_bit, 10
breq nxt_byte
tst cnt_bit
brne data_t
s_bit:
cbi PORTD,PD1
inc cnt_bit
reti
data_t:
cpi cnt_bit, 9
breq p_bit
ror txtmp
rol temp
rol temp
out PORTD, temp;
[7]->C->[0]->[1]->PD1
inc cnt_bit
reti
p_bit:
sbi PORTD,PD1
inc cnt_bit
cp cnt_tx, len_t
breq fin
reti
nxt_byte:
tst cnt_tx
breq len_tx
cp cnt_tx, dat_t
breq sum_tx
clr cnt_bit
ld txtmp, Z+
inc cnt_tx
add sum_t, txtmp
reti
sum_tx:
clr cnt_bit
mov txtmp, sum_t
inc cnt_tx
reti
len_tx:
clr cnt_bit
mov txtmp, len_t
inc len_t
mov dat_t, len_t
inc cnt_tx
inc len_t
reti
fin:
clr txden
clr cnt_tx
clr len_t
ldi ZL, addr+shft
reti
UART_RXC:
sbic USR, FE
rjmp err
sbic USR, 3
rjmp err
in temp, UDR
tst cnt
brne data_r
cpi temp, strt
brne err
inc cnt
reti
data_r:
cpi cnt, 1
breq len
cp cnt, len_r
breq check
st Y+, temp
add sum_r,temp
inc cnt
reti
check:
dec cnt
cp sum_r, temp
brne err
loop:
ld temp, -Y
com temp
std Y+shft, temp
dec cnt
tst cnt
brne loop
inc txden
clr sum_r
ldi YL, addr
ldi txtmp, strt
dec len_r
mov len_t, len_r
reti
err:
clr cnt
clr sum_r
ldi YL, addr
reti
len:
mov len_r, temp
inc len_r
reti
|